The invention relates to a transistor arrangement, an integrated circuit and a method for operating field effect transistors.
The noise of a field effect transistor (in particular MOSFET, “metal oxide semiconductor field effect transistor”) limits the accuracy of an electrical circuit. This is problematic when a signal having a small amplitude occurs in such a circuit. Therefore, the performance of an analog circuit is limited by the phenomenon of noise.
The low-frequency noise of a MOS transistor is caused by statistical loading or unloading of defect states at the interface between the channel region and the gate insulating region of the field effect transistor. At low frequencies, this mechanism supplies the dominant contribution to the noise. On account of their localization the defects are also often referred to as interface states. Predominantly those defects whose energy level lies close to the (quasi) Fermi level of the charge carriers contributing to the current flow contribute to the low-frequency noise. Other interface states whose energy level is significantly higher or lower are either completely occupied or completely unoccupied and thus do not contribute to the noise, cf. S. Christensson, I. Lundström, and C. Svensson, “Low frequency noise in MOS transistors—I theory,” Solid-St. El. 11, pp. 791-812, 1968.
R. Brederlow, W. Weber, R. Jurk, C. Dahl, S. Kessel, J. Holz, W. Sauert, P. Klein, B. Lemaitre, D. Schmitt-Landsiedel, and R. Thewes, “Influence of fluorinated gate oxides on the low frequency noise of MOS transistors under analog operation,” in Proceedings of the 28th European Solid-State Device Research Conference, pp. 472-5, 1998 discloses suppressing low-frequency noise by means of optimizing the fabrication process for the field effect transistors. This exploits the fact that the magnitude of the low-frequency noise critically depends on the quality of the interface between channel region and gate insulating layer. However, narrow limits are imposed on the technological optimization possibilities.
A further method for reducing the low-frequency noise is based on setting the operating point of the field effect transistors such that the low-frequency noise is minimized. By way of example, it is known that choosing the operating point within the framework of those operating points which are suitable for analog circuit technology permits a reduced noise power to be achieved, cf. S. Christensson, I. Lundstrom, and C. Svensson, “Low frequency noise in MOS transistors—I theory,” Solid-St. El. 11, pp. 791-812, 1968. If Vg designates the gate voltage, Vt designates the threshold voltage and Vd designates the drain voltage of a field effect transistor, then Vg−Vt=100 mV to 1V and Vd>VgVt is a suitable choice. With this method, however, there is the restriction of the degrees of freedom in the circuit design from other standpoints, such as, e.g. power consumption, modulation range, bandwidth. Furthermore, the noise reduction that can be achieved by means of this method is small.
Since low-frequency noise voltages or noise currents in a MOSFET are inversely proportional to the root of the active area thereof, cf. S. Christensson, I. Lundstrom, and C. Svensson, “Low frequency noise in MOS transistors—I theory,” Solid-St. El. 11, pp. 791-812, 1968, there is the possibility of reducing the low-frequency noise of a circuit by choosing the component areas to be sufficiently large. With this method, there is the increased area taken up. Moreover, an increased power consumption may result, particularly if the bandwidth of the circuit cannot be reduced, since then only the widths, but not the lengths of the transistors are permitted to be increased. The current consumption of the circuit or of the paths in which the relevant transistors are operated rises approximately proportionally to the width of the relevant transistors. Furthermore, all the capacitive loads that occur in a predetermined circuit rise the input capacitance of sensitive amplifier circuits.
DE 10001124 C1 to I. Bloom, and Y. Nemirowsky, “1/f noise reduction of metal-oxide-semiconductor transistor by cycling from inversion to accumulation,” Appl. Phys. Lett. 58, pp. 1664-6, 1991 disclose that the low-frequency noise of a transistor can be reduced if the quasi Fermi level at the interface is periodically altered.
DE 10001124 C1, S. L. J. Gierkink, E. A. M. Klumperink, E. Van Tuijl, and B. Nauta, “Reducing MOSFET 1/f noise and power consumption by ‘switched biasing’,” in Proceedings of the 28th European Solid-State Circuits Conference, pp. 154-7, 1999 describe circuitry methods for reducing the low-frequency noise of MOSFETs. The method described in S. L. J. Gierkink, E. A. M. Klumperink, E. Van Tuijl, and B. Nauta, “Reducing MOSFET 1/f noise and power consumption by ‘switched biasing’,” in Proceedings of the 28th European Solid-State Circuits Conference, pp. 154-7, 1999 is restricted, however, to circuits in which the transistors are periodically switched on and off. This is not desirable, however, in many analog circuits since continuous signals are intended to be processed.
DE 44 35 305 A1 discloses a signal integrator operated with double sampling speed.
US 2003/0128776 A1 discloses a method and a device for reducing DC offsets in a communication system.
S. L. J. Gierkink et al. “Intrinsic 1/f Device Noise Reduction and Its Effect on Phase Noise in CMOS Ring Oscillators” In: IEEE Journal of Solid-State Circuits, 1999, Vol. 34, No. 7, pp. 1022-1025 discloses intrinsic reduction of 1/f noise and its effect on phase noise in CMOS ring oscillators.
E. Klumpernik et al. “Reducing MOSFET 1/f Noise and Power Consumption by Switched Biasing” In: IEEE Journal of Solid-State Circuits, 2000, Vol. 35, No. 7, pp. 994-1001 discloses a method for reducing 1/f noise and the power consumption in a MOSFET by means of switched biasing.
A mismatch of MOS transistors limits the resolution of circuits. This is the case if said circuits have to process very small signals. Consequently, the performance primarily of analog circuits is limited on account of these phenomena. Manufacturing tolerances (mismatch) of MOS transistors are also caused by the fluctuation of the dopant concentration in the transistor channel and in many cases constitute a great obstacle to the miniaturization of analog circuits.
Precise analog circuits, which are thus susceptible to manufacturing tolerances, are usually constructed in differential fashion. In this case, the transistors important for the function of the circuits (but not necessarily the transistors used for a current source) are doubly present, the pairs of transistors in each case processing signals that are different in their sign but are of identical type in terms of magnitude and phase. For the performance of the analog circuit, it is of crucial importance that the manufacturing tolerances between these transistor pairs become as small as possible.
Various methods are proposed in Enz, C C, Temes, G “Circuit techniques for reducing the effects of op-amp imperfections: auto zeroing, correlated double sampling and chopper stabilization”, Proceedings of the IEEE, Vol. 4, No. 11, September 1996 for reducing the manufacturing tolerances in analog circuits. Firstly, it is possible to enlarge the area of a transistor and to implement a centered layout. In the case of this method, the area of the transistors used has to be enlarged to an extent such that it satisfies the mismatch requirements made of the respective circuit. This is often associated not only with circuitry disadvantages but also with higher manufacturing costs. Furthermore, Enz, CC, Temes, G “Circuit techniques for reducing the effects of op-amp imperfections: auto zeroing, correlated double sampling and chopper stabilization”, Proceedings of the IEEE, Vol. 4, No. 11, September 1996 proposes autozeroing (for example correlated double sampling) and chopper stabilization.
A description is given below of the floating body effect and the self-heating effect, which can occur in partially depleted (PD) and in fully depleted (FD) SOI transistors (“silicon on insulator”) in CMOS technology. These effects have an influence on the circuit design in particular of analog circuits.
With regard to the future development of semiconductor technology, alterations are to be expected away from conventional bulk CMOS processes toward SOI processes, and moreover toward double or triple gate transistor architectures. This expectation is evident e.g. from the International Technology Roadmap for Semiconductors, ITRS 2001.
Despite the advantages of SOI CMOS transistor technology compared with bulk CMOS transistor technology (for example the reduction of parasitic capacitances, the possibility of better diffusion resistances and capacitances, the better device insulation, whereby latch-up effects and substrate coupling effects are reduced, etc.), integrated SOI circuits using analog circuit technology have been investigated only little heretofore, see Tihanyi et al. “Properties of ESFI MOS transistors due to the floating substrate and the finite volume”, IEEE Trans. Electron Devices, Vol. ED-22, p. 1017, 1975.
One problem of SOI field effect transistors is the floating body effect inherent to them, which leads to a kink effect in the case of the drain current. MOS transistors which are processed on SOI films, so that the channel region is partially depleted of charge carriers, or for example a double gate transistor on an SOI film, a vertical transistor on an SOI film (FinFET), etc., are exposed to the floating body effect, see Tihanyi et al. “Properties of ESFI MOS transistors due to the floating substrate and the finite volume”, IEEE Trans. Electron Devices, Vol. ED-22, p. 1017, 1975, Chan et al. “Comparative Study of Fully Depleted and Body-Grounded Non Fully Depleted SOI MOSFETs for High performance analog and Mixed Signal Circuits”, IEEE Trans. On Electron Devices, Vol. ED-42, No. 11, p. 1975, 1995.
The kink effect is brought about by the injection of holes or electrons into the floating substrate of an n-MOS transistor or of a p-MOS transistor on an SOI film. For an n-MOSFET in SOI technology, said holes are generated by means of impact ionization (clearly ionization through charge carrier introduction) into a region with a high electric field near the drain. Once they have been generated, the holes migrate into the region in which the electrical potential is lowest, that is to say in the direction of the floating substrate. Accumulation of holes increases the floating substrate potential until the substrate-source junction is sufficiently biased, for compensating for the current generated by hole generation. The accumulated charge in the body depends on the previous state of the transistor (that is to say its history), on process parameters, device dimension, supply voltage, temperature, slew rate and switching frequency.
The increase in the substrate potential leads to a reduction of the threshold voltage and results in a kink in the output characteristic curve or characteristic, as a result of which the gain of analog amplifiers and the constancy of current sources are impaired.
Another feature of SOI technology compared with bulk MOSFET technology is that the self-heating of individual devices is not negligible. This results from the poor thermal conductivity of the buried silicon oxide layer arranged beneath a silicon layer of an SOI substrate, so that the channel temperature of the SOI device may rise by tens of ° C. above the temperature at normal operation. The insulating substrate forms a thermal barrier, so that the heat generated by the operated device cannot simply be transferred to the substrate. The thermal conductivity of silicon oxide (SiO2) is a few orders of magnitude worse than that of bulk silicon. Therefore, in contrast to a bulk MOS transistor, significant self-heating can occur in the case of a MOS transistor on an SOI film. This self-heating occurs in any type of transistor structure which has a poor thermal coupling between the channel region and heat sinks, such as the bulk silicon or even the housing (e.g. all SOI or double or triple gate concepts).
If the device heats up, the mobility of charge carriers decreases in the channel region, which in turn reduces the drain current. Consequently, the device characteristic is significantly modified, with negative output conductivity, as can often be observed at high drain currents.
Thermal effects are in most cases not significant for digital circuits, on account of the low average energy dissipation, and by virtue of the fact that clock frequencies normally lie sufficiently far above thermal time constants. However, analog circuits can be significantly influenced by self-heating effects. The output conductivity can be low or even negative at low frequencies and can then rise with the frequency, which leads to unforeseen gain and phase variations. Interacting devices that adjoin one another may be at different temperatures, which may lead to a thermally induced mismatch. The temperature gradients which result from the self-heating effect and the thermal coupling effect lead to non-isothermal conditions and therefore to malfunctions, see Tenbroek et al. “Impact of Self-Heating and Thermal Coupling on Analog Circuits in SOI CMOS”, IEEE Journal of Solid-State Circuits, Vol. 33, No. 7, p. 1037, 1998.
Possibilities for alleviating floating body effects of a MOS transistor on an SOI film are known, see Wei et al. “Minimizing Floating-Body-Introduced Threshold Voltage Variation in Partially Depleted SOI CMOS”, IEEE Electron Device Letters, Vol. 17, No. 8, 1996. Among these possibilities, the body contact method appears to be the only circuit-oriented possibility. All the other concepts are related to device engineering. The body potential in a partially depleted SOI transistor is kept constant by the body contact, although the problem occurs as to how the system configuration can be optimized given simultaneous minimization of the effect of stray resistance and stray capacitance between the body contact path and the active region. Furthermore, it is known that the effectiveness of hole absorption falls rapidly if the channel width is increased. In particular, the physical definition of the contact to the FinFET or to the planar double gate transistor requires tricky lithography.
Fully depleted (FD) SOI devices in which an ultra thin silicon body of an SOI substrate having a thickness of 10 nm to 30 nm is used are naturally a good choice for analog/mixed signal applications, since they suppress the kink effect, see Colionge “Silicon-on-Insulator Technology: Material to VLSI”, Norwel, Mass.: Kluwer, p. 139-141, 1991. However, even fully depleted device structures cannot prevent self-heating effects, and it is necessary to take account of the small process margin of FD devices with regard to the threshold voltage control, and also a loss of area. Furthermore, the high inherent body resistance and the high inherent body capacitance which are introduced by the body contact are problematic, and the floating body effects are far more serious in an analog design.
Even advanced double and triple gate concepts suffer from self-heating and, depending on how they are constructed, they may also be exposed to charge accumulation effects such as the kink effect in partially depleted SOI substrates.